The prior art recognizes several ways to form semiconductor memory cells using a field effect transistor (FET) formed on a substrate, with a source and drain region connected by a channel, the current in the channel being controllable with gates disposed over the channels. One type of cell uses an extra floating gate to control current flow in the cell so as to store a logical one or zero. The floating gate is charged by applying a higher than normal voltage to the selected cell so as to tunnel electrons to the otherwise insulated floating gate through a thin area in the insulating oxide. The electrons are trapped in the floating gate and, thus, keep it charged even if all electric power is removed from the cell. Hence, such floating gate cells are nonvolatile. However, the drawback to this approach is that one must use a higher than normal voltage to reprogram or write the cell. In addition, each time the tunneling process is used the thin oxide deteriorates a bit so that the cell has a limited lifespan, typically about 10,000 cycles.
Another type of memory cell comprises a bistable circuit formed usually from six FET devices. Such a circuit can be switched between two stable states, to represent a logical one or zero, by the application of a normal voltage. The lifespan of the circuit is not limited and switching times, and therefore write times, are much faster than that needed to charge a floating gate. The drawback of these circuits is that they require a lot of space and further are volatile, losing the stored information upon a power failure.
The prior art has contemplated combining the advantages of the above described cells by using floating gate arrangements added to the bistable circuits so as to store the logical information during power failures. A suitable detection circuit responds to a loss of power by applying a quick, higher than normal, voltage pulse to the circuit in such a way as to charge one of two different floating gates depending on the state of the bistable circuit. The two floating gates are positioned to affect the threshold voltage of two different FET's in the bistable circuit respectively so that, when power is restored, the circuit turns on in the same state it had when it turned off. The logical information is thereby recreated and the memory array formed from these cells is non-volatile. Since the floating gates are charged and discharged only during power lapses, rather than at each rewrite, the lifespan is considerably improved. And since each rewrite is done with the simple switching of fast FET's at normal voltages, high speed is retained. But with six FET's, two floating gates, and two thin oxides, complexity and size become the drawback of this approach.
The present invention allows the construction of a nonvolatile bistable memory cell that needs only one floating gate and only three or four FET's, thus substantially reducing complexity and size.